The present invention relates to a semiconductor device composed of a plurality of semiconductor processing sections connected in cascade, and also relates to a display device module using the semiconductor device.
FIG. 20 illustrates the system structure of semiconductor processing sections in a conventional liquid crystal display device module. As shown in FIG. 20, a plurality of source drivers 51 and gate drivers 52 made of LSIs (large scale integrated circuits) are mounted as source drivers S and gate drivers G, respectively, on a liquid crystal panel 54 in such a state in which they are incorporated in TCPS (tape carrier packages). These source drivers S drive source buslines (not shown) in the liquid crystal panel 54, while the gate drivers G drive gate buslines (not shown) therein.
Terminals (a group of terminals) of each of the source drivers 51 and gate drivers 52, which are located on the liquid crystal panel 54 side, are electrically connected to a terminal (not shown) formed by an ITO (indium tin oxide) on the liquid crystal panel 54 through the lines in the TCPs 53. For instance, electrical connection of the terminals is achieved by thermo-compression bonding with an ACF (anisotropic conductive film) therebetween. Moreover, terminals of each of the source drivers 51 and gate drivers 52, which are located on a flexible substrate 55 side, are electrically connected to the lines on the flexible substrate 55 through the lines in the TCPs 53 by the above-mentioned ACF or soldering.
Therefore, supply of display-use data signals to the source drivers 51 from a controller circuit 56 and supply of various control signals and power (GND, Vcc) to the source drivers 51 and the gate drivers 52 are performed through the lines on the flexible substrate 55 and the lines on the TCPs 53.
Here, for the source drivers S, a total of eight source drivers, i.e., the first source driver S(1) to the eighth source driver S(8), are provided. Meanwhile, for the gate drivers G, a total of two gate drivers, i.e., the first gate driver G(1) and the second gate driver G(2), are provided.
Regarding the first source driver S(1) to the eighth source driver S(8), eight identical source drivers 51 are connected in cascade to supply the display-use data signals R, G, B, a start pulse input signal SSPI and a clock signal SCK output from the controller circuit 56.
Besides, regarding the first gate driver G(1) and the second gate driver G(2), two identical gate drivers 52 are connected in cascade to supply a clock signal GCK and a start pulse input signal GSPI output from the controller circuit 56. FIG. 21 is an enlarged view of the structure of the terminals of the controller circuit 56 that output various signals.
The number of pixels in the liquid crystal panel 54 is, for example, 1024 pixelsxc3x973 (RGB) [on the source side]xc3x97768 pixels [on the gate side]. Therefore, each of the source drivers 51 of the first source driver S(1) to the eighth source driver S(8) displays 64 gray scales, and drives 128 pixelsxc3x973 (RGB).
FIG. 22 shows the structure of the source driver 51. As illustrated in FIG. 22, the source driver 51 includes a shift register circuit 61, a data latch circuit 62, a sampling memory circuit 63, a hold memory circuit 64, a reference voltage generator circuit 65, a DA converter circuit 66, and an output circuit 67.
The shift register circuit 61 includes, for example, a plurality of latch circuits (not shown) connected in cascade. For the explanation of the operation, assuming that this source driver 51 is referred to as the first source driver (1) of the first stage, the shift register circuit 61 shifts (transmits/transfers) the start pulse input signal SSPI, which was synchronized with a horizontal synchronizing signal of the display-use data signals R, G, B, output from the terminal SSPI of the controller circuit 56 and input to the input terminal SSPin of the source driver 51, by the clock signal SCK which was output from the terminal SCK of the controller circuit 56 and input to the input terminal SCKin of the source driver 51.
The start pulse input signal SSPI shifted by the shift register circuit 61 is output from the output terminal SSPout of the source driver 51 so that the output of the final stage is output as the start pulse output signal SSPO, and then input as the start pulse input signal SSPI to the input terminal SSPin of the source driver 51 of the second source driver S(2) of the next stage. In this manner, the start pulse input signal SSPI is shifted up to the final stage of the shift register circuit 61 of the source driver 51 of the eighth source driver S(8) of the eighth stage.
Moreover, the clock signal SCK input to the shift register circuit 61 is also output from the output terminal SCKout of the source driver 51, input to the input terminal SCKin of the source driver 51 of the second source driver S(2) of the next stage, and transferred up to the source driver 51 of the eighth source driver S(8).
On the other hand, 6-bit display-use data signals R, G, B output from the terminals R1 to R6, G1 to G6 and B1 to B6 of the controller circuit 56 are synchronized with the rise of a clock signal/SCK (the inverted signal of the clock signal SCK), serially input to the input terminals R1in to R6in, G1in to G6in and B1in to B6in of the source driver 51, respectively, temporarily latched by the data latch circuit 62 and then forwarded to the sampling memory circuit 63.
Furthermore, the display-use data signals R, G, B which were serially input to the input terminals R1in to R6in, G1in to G6in and B1in to B6in of the source driver 51 are output from the output terminals R1out to R6out, G1out to G6out and B1out to B6out of this source driver 51, respectively, and forwarded to the source driver 51 of the second source driver S(2) of the next stage. In the same manner they are successively transferred up to the source driver 51 of the eighth source driver S(8).
The sampling memory circuit 63 samples display-use data signals (a total of 18 bits, i.e., 6 bits for each of R, G, B) sent by time division with the output signal of each stage of the shift register circuit 61, and stores them until a latch signal LS output from the terminal LS of the controller circuit 56 is input to the terminal LS of the source driver 51.
These display-use data signals are then input to the hold memory circuit 64 where the display-use data signals input from the sampling memory circuit 63 are latched by the latch signal LS upon the input of the display-use data signals corresponding to one horizontal period of the display-use data signals R, G, B, held until the display-use data signals corresponding to the next horizontal period are input to the hold memory circuit 64 from the sampling memory circuit 63 and then output.
The reference voltage generator circuit 65 generates 64 levels voltages used for, for example, gray-scale display by resister division from reference voltages which are output from the terminals Vref1 to Vref9 of the controller circuit 56 and input to the terminals Vref1 to Vref9 of the source driver 51.
The DA converter 66 converts each of the 6-bit display-use data signals (digital) R, G, B input from the hold memory circuit 64 into an analog signal, and outputs the resultant signal to the output circuit 67. The output circuit 67 amplifies 64 levels analog signals, and outputs them to the terminal (not shown) of the liquid crystal panel 54 from the output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128. The output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128 correspond to the display-use data signals R, G, B, respectively. Each of the Xo, Yo and Zo includes 128 terminals.
The terminal Vcc and the terminal GND of the source driver 51 are power-supply terminals connected to the terminal Vcc and terminal GND of the controller circuit 56, and supplied with a power supply voltage and grand potential. Note that, each of the buffer circuits provided in the input section and output section of the source driver 51 are omitted in FIG. 22.
The above descriptions explain the structure and operation of a group of source drivers S for 64-gray-scale display. Regarding the gate driver 52 constituting the gate driver G, since it has basically the same structure as the source driver 51 of the source driver S, the explanation thereof will be omitted here.
By the way, nowadays, there is a tendency to increase the number of pixels and the resolution of the liquid crystal display device modules. For the increases of the number of pixels and the resolution, the source drivers 51 and gate drivers 52 need to increase the data transfer rate of the display-use data signals R, G, B, i.e., to perform the operations with a high-frequency clock. This is particularly apparent for the source drivers 51 in comparison with the gate drivers 52.
However, the source drivers 51 as the semiconductor processing sections employed in the above-described conventional liquid crystal display module suffer from the following problem and can not sufficiently satisfy the need for the increases of the number of pixels and the resolution.
More specifically, in the above-described conventional liquid crystal display module, a plurality of identical source drivers 51 are used by connecting them in cascade, and the display-use data signals R, G, B are input only to the source driver 51 of the first source driver S(1) of the first stage. Meanwhile, the respective source drivers 51 of the other source drivers S located after the first source driver S(1) employ a self-transfer system which successively transfers the display-use data signals R, G, B through the source drivers 51.
In this case, for example, in the source driver S for displaying 64 gray scales, a very high data transfer rate of 65 MHz is needed for an XGA (1024xc3x97RGBxc3x97768) panel which handles a total of 18 data (6 bitsxc3x97three kinds: R, G, B) corresponding to R, G, B. Furthermore, a higher transfer rate of 95 MHz is required for a high-definition SXGA (1280xc3x97RGBxc3x971024) panel. It is thus necessary to successively self-transfer the display-use data signals at a higher data transfer rate as the definition is increased.
However, in order to ensure the specifications (data setup/hold time) for the data fetching timing in the source driver S of the next stage by the same transfer-use clock signal SCK, it is necessary to fetch the next display-use data signals within a cycle of the clock signal SCK as shown in FIG. 23. However, in the case where the signals are self-transferred at a higher rate, they are easily affected by the capacity of the line, etc., and hence it is difficult to ensure the specifications for the data fetching timing and the image quality of high-definition display may deteriorate.
Furthermore, with the conventional technique, in the case where the signals are self-transferred at a higher data transfer rate, it is difficult ensure the duty ratio (the ratio between a high period and a low period) of the transfer-use clock signal SCK in the source driver S, and hence the operating frequency may decrease and the image quality of high-definition display may deteriorate.
Considering the above problems, it is an object of the present invention to widen the operating frequency range of the clock signal SCK and provide a semiconductor device capable of realizing a display image of highly reliable image quality and a display device module using the semiconductor device.
In order to achieve the above object, a semiconductor device of the present invention includes:
a plurality of semiconductor processing sections which are connected in cascade and perform data processing by a self-transfer system in which a plurality of signals input to the semiconductor processing section of the first stage are successively transferred through the semiconductor processing section to other semiconductor processing section;
dividing means, provided in an input section of each of the semiconductor processing sections, for converting serial data to be transferred into parallel data by dividing the serial data of one channel into N channels (N is a natural number) by using both of the leading and trailing edges of a first clock signal as data fetching timing; and
synthesizing means, provided in an output section of each of the semiconductor processing sections, for synthesizing the one-channel serial data from the divided N-channel parallel data. In the above semiconductor device, N is preferably 2 or 4 to facilitate the fabrication of the semiconductor processing sections.
With this structure, in each of the semiconductor processing sections, the serial data as one-channel display-use data signals is divided into N channels, for example, 2 or 4-channel parallel data by fetching the serial data at both of the leading and trailing edges of the first clock signal by the dividing means provided in the input section. For instance, the parallel data is used for display. In the synthesizing means provided in the output section, the one-channel serial data is synthesized again from the parallel data, i.e., the parallel data is brought back into the serial data, and the serial data is output. Thus, the signals are transferred between the semiconductor processing sections by the self-transfer system.
In this structure, therefore, the frequency of the first clock signal can be reduced to 1/N of the data transfer rate (data frequency) of the serial data, for example, reduced to a half for 2 channels. Additionally, in the above structure, with the reduction of the frequency of the first clock signal, the transfer timing of the display-use data signals to be successively transferred to the semiconductor processing section of the next stage can be controlled, for example, delayed by the synthesizing means, and hence the specifications (data setup/hold time) for the data fetching timing of the display-use data signals can be easily ensured in each of the semiconductor processing sections.
Consequently, according to the above structure, for example, even when the semiconductor device is incorporated as a drive device for a liquid crystal display device into a liquid crystal display device module and the data frequency of the serial data such as the display-use data signals is increased to achieve a high-definition liquid crystal display device module, the duty ratio of the transfer-use first clock signal can be ensured in each semiconductor processing section without causing problems and the specifications for the data fetching timing can be easily ensured, thereby achieving a display image of highly reliable quality with the widening of the operating frequency range of the clock signal and the decrease of the operating frequency of the clock signal.
In order to achieve the above object, a display device module of the present invention includes any one of the semiconductor devices and a display section driven by the semiconductor device. In this display device module, the display section may be a liquid crystal display section.
According to this structure, since the semiconductor processing section can certainly meet a higher (faster) data frequency of the display-use data signals to achieve a high definition, the quality of the display image on the display section, for example, the liquid crystal display section, using the display-use data signals can be improved in a stable manner while ensuring high definition.